1. Field of the Invention
This invention generally relates to differential circuits and receiving devices having the same used for small-amplitude and current-mode high-speed serial digital transmission signals, and more particularly, to a differential circuit having an input circuit and a buffer circuit included in a receiving device used for receiving high-speed serial digital transmission signals. The input circuit needs to handle a rail-to-rail input common-mode range having a terminal common-mode voltage near the ground level voltage to the power supply voltage and a differential output buffer circuits having a constant common-mode potential, that is independent of the input common-mode voltage are necessary for processing the high-speed signals inside the chip.
2. Description of the Related Art
Conventionally, the interface standards for the digital signals such as the transistor-transistor logic: TTL (2.0/0.8) and the complementary metal-oxide semiconductor: CMOS (3.3/0.0) have been used in the serial digital transmission. However, these standards are standardized for the digital signals that have relatively large voltage amplitudes, and there is a problem in that signal transmission delay is relatively large. Therefore, it is difficult to realize the high-speed serial digital transmission, which is demanded in these years, between the devices with the use of the above-mentioned standards.
In order to solve the aforementioned problem, small-voltage swing and current-mode differential transmission standards have been proposed in recent years. An example of the standards is LVDS (low Voltage Differential Signaling).
The LVDS standard only specifies the use of a differential current driver and terminal impedance. Therefore, the input differential circuit that meets the LVDS standard has to operate at an arbitrary common-mode terminal voltage. According to the standard, a current driver is used for a transmitting circuit (hereinafter, referred to as LVDS transmitter) drives a signal that meets the LVDS standard (hereinafter, referred to as LVDS signal) so that 350 mV of amplitude may be available as a terminal voltage, when the terminal impedance of 100 Ω is connected. On the other hand, the receiving circuit of the LVDS signal (hereinafter, referred to as LVDS receiver) is configured so that a terminal voltage difference of approximately 350 mV can be received, corresponding to the common-mode terminal voltage of 0 to 2.4 V. That is to say, if the power supply voltage Vcc of 2.5 V is set, the amplifier circuit in the input circuit of the LVDS receiver is to operate the common-mode input signal, which is substantially equal to the power supply voltage. The rail-to-rail operation denotes the operation of the common-mode input signals substantially equal to the power supply voltage.
Conventionally, as a structure of a rail-to-rail differential amplifier circuit with the use of CMOS technology, a topology has been proposed so that the limits of the both common-mode operation ranges may be compensated by connecting the differential amplifier circuit of an N-channel element in parallel with the differential amplifier circuit of a P-channel element.
Under the circumstances, the output from the amplifier circuit arranged as the input circuit is demanded to have desirable signal quality for the amplifier circuit provided in the later stage. That is, it is preferable that the differential output from the amplifier circuit of the input circuit has a constant common-mode potential to be independent of the input common-mode voltage in order to operate the high-speed signals inside the chip. Moreover, an appropriate buffer circuit has to be included to drive the load inside the chip.
For example, U.S. Pat. No. 6,320,422 discloses the technique of feed backing the output voltage in the buffer circuit to control and stabilize the differential output in the differential amplifier circuit. Hereinafter, the aforementioned patent will be referred to as a conventional technique 1, and will be described with reference to FIG. 1.
Referring to FIG. 1, the conventional technique 1 is configured to include a differential amplifier circuit having an N-channel differential amplifier circuit 801 and a P-channel differential amplifier circuit 813, a complementary source follower circuit 826 and a complementary source follower 828. Outputs (806 and 818) from the differential amplifier circuit are input into the complementary source follower circuit 826, and in the same manner, outputs (808 and 820) from the differential amplifier circuit are input into the complementary source follower 828. The above-mentioned two complementary source follower circuits 826 and 828 serve as the buffer circuits that drive the internal loads.
The N-channel differential amplifier circuit 801 includes an N-channel differential element 802, active loads 812 and 810, and a constant current source 804. The N-channel differential element 802 has a pair of N-channel MOS transistors (field-effect transistors are preferable. Hereinafter, simply referred to as transistors). The active loads 812 and 810 are the loads of the N-channel differential element 802. The constant current source 804 is connected to the N-channel differential element 802. In the same manner, the P-channel differential amplifier circuit 813 includes a P-channel differential element 814, active loads 822 and 824, and a constant current source 816. The P-channel differential element 814 has a pair of P-channel MOS transistors. The active loads 822 and 824 are the loads of the P-channel differential element 814. The constant current source 816 is connected to the P-channel differential element 814.
In the above-mentioned configuration, an output node 830 of the complementary source follower circuit 826 is connected to the active loads 810 and 822 respectively, which are composed of the N-channel MOS transistors. That is, the both edges of the voltages of the active loads 810 and 822 are controlled to feed back according to the output voltage of the complementary source follower circuit 826. In the same manner, an output node 832 of the complementary source follower circuit 828 is connected to the active loads 812 and 824 respectively, which are composed of the N-channel MOS transistors. That is, the both terminal voltages of the active loads 812 and 824 are controlled to feed back according to the output voltage of the complementary source follower circuit 828. This can prevent the operation points of the active loads 810, 812, 822, and 824 from shifting from the linear region into the saturation region. The operation is thus configured to always operate in the linear region, which prevents a non-linear operation of the differential output so as to stabilize the differential outputs.
However, with the configuration as disclosed in the conventional technique 1, it is impossible to stabilize the common-mode potentials of the output voltages from the two complementary source follower circuits provided in the output circuit, if the input common-mode voltage makes the two complementary source follower circuits operate in different modes. In addition, if the output voltage is configured to feed back as disclosed in the conventional technique 1, there may arise an oscillation by switching the output voltage at a high speed.